As reductions in device scaling continue channel mobility issues become more problematic, particularly for NMOS transistors. It has been found that (110) silicon (Si) boosts hole mobility, thereby improving PMOS performance over (100) Si. However, electron mobility on (110) Si degrades by a comparable amount to the PMOS boost. Stress liners and embedded stressors may be used to improve electron mobility. However, as CMOS scaling reaches smaller and smaller pitches, such as 22 nanometer (nm) node and beyond, the smaller pitch between gates significantly reduces stressor volume, and, therefore, stressor benefit. Therefore, at smaller pitches, the benefit of stress liners and embedded stressors does not overcome the large mobility penalty in the (110) Si substrate.
A need therefore exists for methodology enabling the formation of a CMOS device with both increased hole mobility for the PMOS device and increased electron mobility for the NMOS device.